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e preliminary jul y 1998 order number: 290580-005 n flexible smartvoltage technology ? 2.7 v C3.6 v read/program/erase ? 12 v v pp fast production programming n 2.7 v or 1.65 v i/o option ? reduces overall system power n high performance ? 2.7 v?3.6 v: 90 ns max access time ? 3.0 v?3.6 v: 80 ns max access time n optimized block sizes ? eight 8-kb blocks for data, top or bottom locations ? up to sixty-three 64-kb blocks for code n block locking ? v cc -level control through wp# n low power consumption ? 10 ma typical read current n absolute hardware-protection ? v pp = gnd option ? v cc lockout voltage n extended temperature operation ? ?40 c to +85 c n flash data integrator software ? flash memory manager ? system interrupt manager ? supports parameter storage, streaming data (e.g., voice) n automated program and block erase ? status registers n extended cycling capability ? minimum 100,000 block erase cycles guaranteed n automatic power savings feature ? typical i ccs after bus inactivity n standard surface mount packaging ? 48-ball m bga* package ? 48-lead tsop package ? 40-lead tsop package n footprint upgradeable ? upgrade path for 4-, 8-, 16-, and 32- mbit densities n etox? vi (0.25 m) flash technology the smart 3 advanced boot block, manufactured on intels latest 0.25 technology, represents a feature- rich solution at overall lower system cost. smart 3 flash memory devices incorporate low volt age capability (2.7 v read, program and erase) with high-speed, low-power operation. several new features have been added, including the ability to drive the i/o at 1.65 v, which significantly reduces system active power and interfaces to 1.65 v controllers. a new blocking scheme enables code and data storage within a single device. add to this the intel-developed flash data integrator (fdi) software, and you have a cost-effective, monolithic code plus data storage solution. smart 3 advanced boot block products will be available in 40- lead and 48-lead tsop and 48-ball bga* packages. additional information on this product family can be obtained by accessing intels www page: http://www.intel.com/design/flash. smart 3 advanced boot block 4-, 8-, 16-, 32-mbit flash memory family 28f400b3, 28f800b3, 28f160b3, 28f320b3 28f008b3, 28f016b3, 28f032b3
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f400b3, 28f800/008b3, 28f160/016b3, 38f320/032b3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1996, 1997,1998 cg-041493 * third-part y brands and names are the propert y of their respective owners
e smart 3 advanced boot block 3 preliminary contents page page 1.0 introduction .............................................5 1.1 smart 3 advanced boot block flash memory enhancements ..............................5 1.2 product overview.........................................6 2.0 product description..............................6 2.1 package pinouts ..........................................6 2.2 block organization .....................................11 2.2.1 parameter blocks ................................11 2.2.2 main blocks .........................................11 3.0 principles of operation .....................11 3.1 bus operation ............................................12 3.1.1 read....................................................13 3.1.2 output disable.....................................13 3.1.3 standby ...............................................13 3.1.4 deep power-down / reset ..................13 3.1.5 write....................................................13 3.2 modes of operation....................................14 3.2.1 read array ..........................................14 3.2.2 read identifier .....................................15 3.2.3 read status register ..........................16 3.2.4 program mode.....................................16 3.2.5 erase mode .........................................17 3.3 block locking.............................................20 3.3.1 wp# = v il for block locking................20 3.3.2 wp# = v ih for block unlocking ............20 3.4 v pp program and erase voltages ..............20 3.4.1 v pp = v il for complete protection .......20 3.5 power consumption ...................................20 3.5.1 active power .......................................21 3.5.2 automatic power savings (aps) .........21 3.5.3 standby power ....................................21 3.5.4 deep power-down mode.....................21 3.6 power-up/down operation.........................21 3.6.1 rp# connected to system reset ........21 3.6.2 v cc , v pp and rp# transitions .............21 3.7 power supply decoupling ..........................22 4.0 electrical specifications..................23 4.1 absolute maximum ratings........................23 4.2 operating conditions..................................24 4.3 capacitance ...............................................24 4.4 dc characteristics .....................................25 4.5 ac characteristics read operations .......28 4.6 ac characteristicswrite operations........30 4.7 program and erase timings .......................31 5.0 reset operations ..................................33 6.0 ordering information..........................34 7.0 additional information .......................36 appendix a: write state machine current/next states.....................................37 appendix b: access time vs. capacitive load...........................................38 appendix c: architecture block diagram ......39 appendix d: word-wide memory map diagrams......................................................40 appendix e: byte wide memory map diagrams......................................................43 appendix f: program and erase flowcharts .45
smart 3 advanced boot block e 4 preliminary revision history number description -001 original version -002 section 3.4, v pp program and erase voltages , added updated figure 9: automated block erase flowchart updated figure 10: erase suspend/resume flowchart (added program to table) updated figure 16: ac waveform: program and erase operations (updated notes) i ppr maximum specification change from 25 m a to 50 m a program and erase suspend latency specification change updated appendix a: ordering information (included 8 m and 4 m information) updated figure, appendix d: architecture block diagram (block info. in words not bytes) minor wording changes -003 combined byte-wide specification (previously 290605) with this document improved speed specification to 80 ns (3.0 v) and 90 ns (2.7 v) improved 1.8 v i/o option to minimum 1.65 v (section 3.4) improved several dc characteristics (section 4.4) improved several ac characteristics (sections 4.5 and 4.6) combined 2.7 v and 1.8 v dc characteristics (section 4.4) added 5 v v pp read specification (section 3.4) removed 120 ns and 150 ns speed offerings moved ordering information from appendix to section 6.0; updated information moved additional information from appendix to section 7.0 updated figure appendix b, access time vs. capacitive load updated figure appendix c, architecture block diagram moved program and erase flowcharts to appendix e updated program flowchart updated program suspend/resume flowchart minor text edits throughout. -004 added 32-mbit density added 98h as a reserved command (table 4) a 1 Ca 20 = 0 when in read identifier mode (section 3.2.2) status register clarification for sr3 (table 7) v cc and v ccq absolute maximum specification = 3.7 v (section 4.1) combined i ppw and i ccw into one specification (section 4.4) combined i ppe and i cce into one specification (section 4.4) max parameter block erase time (t whqv2 /t ehqv2 ) reduced to 4 sec (section 4.7) max main block erase time (t whqv3 /t ehqv3 ) reduced to 5 sec (section 4.7) erase suspend time @ 12 v (t whrh2 /t ehrh2 ) changed to 5 s typical and 20 s maximum (section 4.7) ordering information updated (section 6.0) write state machine current/next states table updated (appendix a) program suspend/resume flowchart updated (appendix f) erase suspend/resume flowchart updated (appendix f) text clarifications throughout -005 m bga package diagrams corrected (figures 3 and 4) i ppd test conditions corrected (section 4.4) 32-mbit ordering information corrected (section 6) m bga package top side mark information added (section 6)
e smart 3 advanced boot block 5 preliminary 1.0 introduction this datasheet contains the specifications for the advanced boot block flash memory family, which is optimized for low power, portable systems. this family of products features 1.65 v C2.5 v or 2.7 vC 3.6 v i/os and a low v cc /v pp operating range of 2.7 vC3.6 v for read, program, and erase operations. in addition this family is capable of fast programming at 12 v. throughout this document, the term 2.7 v refers to the full voltage range 2.7 vC3.6 v (except where noted otherwise) and v pp = 12 v refers to 12 v 5%. section 1.0 and 2.0 provide an overview of the flash memory family including applications, pinouts and pin descriptions. section 3.0 describes the memory organization and operation for these products. sections 4.0 and 5.0 contain the operating specifications. finally, sections 6.0 and 7.0 provide ordering and other reference information. 1.1 smart 3 advanced boot block flash memory enhancements the smart 3 advanced boot block flash memory features enhanced blocking for easy segmentation of code and data or additional design flexibility program suspend to read command v ccq input of 1.65 vC2.5 v on all i/os. see figures 1 through 4 for pinout diagrams and v ccq location maximum program and erase time specification for improved data storage. table 1. smart 3 advanced boot block feature summary feature 28f008b3, 28f016b3, 28f032b3 (1) 28f400b3 (2), 28f800b3, 28f160b3, 28f320b3 reference v cc read voltage 2.7 vC 3.6 v section 4.2, 4.4 v ccq i/o voltage 1.65 vC2.5 v or 2.7 vC 3.6 v section 4.2, 4.4 v pp program/erase voltage 2.7 vC 3.6 v or 11.4 vC 12.6 v section 4.2, 4.4 bus width 8-bit 16 bit table 3 speed 80 ns, 90 ns, 100 ns, 110 ns section 4.5 memory arrangement 1024 kbit x 8 (8 mbit), 2048 kbit x 8 (16 mbit), 4096 kbit x 8 (32 mbit) 256 kbit x 16 (4 mbit), 512 kbit x 16 (8 mbit), 1024 kbit x 16 (16 mbit) 2048 kbit x 16 (32 mbit) section 2.2 blocking (top or bottom) eight 8-kbyte parameter blocks and seven 64-kbyte blocks (4-mbit) or fifteen 64-kbyte blocks (8-mbit) or thirty-one 64-kbyte main blocks (16-mbit) sixty-three 64-kbyte main blocks (32-mbit) section 2.2 appendix d locking wp# locks/unlocks parameter blocks all other blocks protected using v pp section 3.3 table 8 operating temperature extended: C40 c to +85 c section 4.2, 4.4 program/erase cycling 100,000 cycles section 4.2, 4.4 packages 40-lead tsop (1) , 48-ball m bga* csp (2) 48-lead tsop, 48-ball m bga csp (2) figure 3, figure 4 notes: 1. 4-mbit and 32-mbit density not available in 40-lead tsop. 2. 4-mbit density not available in m bga* csp.
smart 3 advanced boot block e 6 preliminary 1.2 product overview intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: v cc for read operation, v ccq for output swing, and v pp for program and erase operation. all smart 3 advanced boot block flash memory products provide program/erase capability at 2.7 v or 12 v [for fast production programming] and read with v cc at 2.7 v. since many designs read from the flash memory a large percentage of the time, 2.7 v v cc operation can provide substantial power savings. the smart 3 advanced boot block flash memory products are available in either x8 or x16 packages in the following densities: (see ordering information for availability.) 4-mbit (4,194,304-bit) flash memory organized as 256 kwords of 16 bits each or 512 kbytes of 8-bits each 8-mbit (8,388,608-bit) flash memory organized as 512 kwords of 16 bits each or 1024 kbytes of 8-bits each 16-mbit (16,777,216-bit) flash memory organized as 1024 kwords of 16 bits each or 2048 kbytes of 8-bits each 32-mbit (33,554,432-bit) flash memory organized as 2048 kwords of 16 bits each or 4096 kbytes of 8-bits each the parameter blocks are located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. the upper two (or lower two) parameter blo cks can be locked to provide complete code security for system initialization c ode. locking and unlocking is controlled by wp# (see section 3.3 for details). the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby un- burdening the microprocessor or microcontroller. the status register indicates the status of the wsm by signifying block erase or word program completion and status. the smart 3 advanced boot block flash memory is also designed with an automatic power savings (aps) feature which minimizes system current drain, allowing for very low power designs. this mode is entered following the completion of a read cycle (approximately 300 ns later). the rp# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see section 3.6). section 3.0 gives detailed explanation of the different modes of operation. complete current and voltage specifications can be found in the dc characteristics section. refer to ac characteristics for read, program and erase performance specifications. 2.0 product description this section explains device pin description and package pinouts. 2.1 package pinouts the smart 3 advanced boot block flash memory is available in 40-lead tsop (x8, figure 1), 48-lead tsop (x16, figure 2) and 48-ball m bga packages (x8 and x16, figure 3 and figure 4 respectively). in all figures, pin changes necessary for density upgrades have been circled.
e smart 3 advanced boot block 7 preliminary a 17 gnd a 20 a 19 a 10 dq 7 dq 6 dq 5 dq 4 v ccq v cc nc dq 3 dq 2 dq 1 dq 0 oe# gnd ce# a 0 a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 we# rp# v pp wp# a 18 a 7 a 6 a 5 a 4 a 3 a 2 a 1 16 m 8 m advanced boot block 40-lead tsop 10 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 0580_01 notes: 1. 40-lead tsop available for 8- and 16-mbit densities only. 2. lower densities will have nc on the upper address pins. for example, an 8-mbit device will have nc on pin 38. figure 1. 40-lead tsop package for x8 configurations advanced boot block 48-lead tsop 12 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 16 v ccq gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 nc a 20 we# rp# v pp wp# a 19 a 18 a 17 a 7 a 6 a 5 21 22 23 24 oe# gnd ce# a 0 28 27 26 25 a 4 a 3 a 2 a 1 32 m 4 m 16 m 8 m 0580_02 note: lower densities will have nc on the upper address pins. for example, an 8-mbit device will have nc on pins 9 and 15. figure 2. 48-lead tsop package for x16 configurations
smart 3 advanced boot block e 8 preliminary a 14 a 15 a 16 a 17 v ccq a 12 a 10 a 13 nc a 11 a 8 we# a 9 d 5 d 6 v pp rp# nc nc wp# a 19 a 21 d 2 d 3 a 20 a 18 a 6 nc nc a 7 a 5 a 3 ce# d 0 a 4 a 2 a 1 a 0 gnd gnd d 7 nc d 4 v cc nc d 1 oe# a b c d e f 13 25 47 68 16m 32m 8m 0580_04 note: 1. shaded connections indicate the upgrade address connections. lower density devices will not have the upper address solder balls. routing is not recommended in this area. a 20 is the upgrade address for the 16-mbit device. a 21 is the upgrade address for the 32-mbit device. 2. 4-mbit density not available in m bga* csp. figure 3. x8 48-ball m bga* chip size package (top view, ball down)
e smart 3 advanced boot block 9 preliminary a 13 a 14 a 15 a 16 v ccq a 11 a 10 a 12 d 14 d 15 a 8 we# a 9 d 5 d 6 v pp rp# d 11 d 12 wp# a 18 a 20 d 2 d 3 a 19 a 17 a 6 d 8 d 9 a 7 a 5 a 3 ce# d 0 a 4 a 2 a 1 a 0 gnd gnd d 7 d 13 d 4 v cc d 10 d 1 oe# a b c d e f 13 25 47 68 16m 32m 8m 0580_03 notes: 1. shaded connections indicate the upgrade address connections. lower density devices will not have the upper address solder balls. routing is not recommended in this area. a 19 is the upgrade address for the 16-mbit device. a 20 is the upgrade address for the 32-mbit device. 2. 4-mbit density not available in m bga* csp. figure 4. x16 48-ball m bga* chip size package (top view, ball down)
smart 3 advanced boot block e 10 preliminary the pin descriptions table details the usage of each device pin. table 2. smart 3 advanced boot block pin descriptions symbol type name and function a 0 Ca 21 input address inputs for memory addresses. addresses are internally latched during a program or erase cycle. 28f008b3: a[0-19], 28f016b3: a[0-20], 28f032b3: a[0-21], 28f800b3: a[0-17], 28f800b3: a[0-18], 28f160b3: a[0-19], 28f320b3: a[0-20] dq 0 Cdq 7 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched. outputs array, identifier and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. dq 8 Cdq 15 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched. outputs array and identifier data. the data pins float to tri-state when the chip is de-selected. not included on x8 products. ce# input chip enable: activates the internal control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. oe# input output enable: enables the devices outputs through the data buffers during a read operation. oe# is active low. we# input write enable: controls writes to the command register and memory array. we# is active low. addresses and data are latched on the rising edge of the second we# pulse. rp# input reset/deep power-down: uses two voltage levels (v il , v ih ) to control reset/deep power-down mode. when rp# is at logic low, the device is in reset/deep power-down mode , which drives the outputs to high-z, resets the write state machine, and minimizes current levels (i ccd ). when rp# is at logic high, the device is in standard operation . when rp# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. wp# input write protect: provides a method for locking and unlocking the two lockable parameter blocks. when wp# is at logic low, the lockable blocks are locked , preventing program and erase operations to those blocks. if a program or erase operation is attempted on a locked block, sr.1 and either sr.4 [program] or sr.5 [erase] will be set to indicate the operation failed. when wp# is at logic high, the lockable blocks are unlocked and can be programmed or erased. see section 3.3 for details on write protection.
e smart 3 advanced boot block 11 preliminary table 2. smart 3 advanced boot block pin descriptions (continued) symbol type name and function v ccq input output v cc : enables all outputs to be driven to 1.8 v C 2.5 v while the v cc is at 2.7 vC3.3 v. if the v cc is regulated to 2.7 vC2.85 v, v ccq can be driven at 1.65 vC2.5 v to achieve lowest power operation (see section 4.4, dc characteristics . this input may be tied directly to v cc (2.7 vC3.6 v). v cc device power supply: 2.7 vC3.6 v v pp program/erase power supply: supplies power for program and erase operations. v pp may be the same as v cc (2.7 vC3.6 v) for single supply voltage operation. for fast programming at manufacturing, 11.4 vC12.6 v may be supplied to v pp . this pin cannot be left floating. applying 11.4 vC12.6 v to v pp can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum (see section 3.4 for details). v pp < v pplk protects memory contents against inadvertent or unintended program and erase commands. gnd ground: for all internal circuitry. all ground inputs must be connected. nc no connect: pin may be driven or left floating. 2.2 block organization the smart 3 advanced boot block is an asymmetrically-blocked architecture that enables system integration of c ode and data within a single flash device. each block can be erased independently of the others up to 100,000 times. for the address locations of each block, see the memory maps in appendix d. 2.2.1 parameter blocks the smart 3 advanced boot block flash memory architecture includes parameter blo cks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an eeprom). by using software techniques, the word- rewrite functionality of eeproms can be emulated. each device contains eight parameter blocks of 8-kbytes/4-kwords (8192 bytes/4,096 words) each. 2.2.2 main blocks after the parameter blocks, the remai nder of the array is divided into equal size main blo cks (65,536 bytes / 32,768 words) for data or code storage. the 4-mbit device contains seven main blocks; 8-mbit device contains fifteen main blo cks; 16-mbit flash has thirty-one main blo cks; 32-mbit has sixty-three main blocks. 3.0 principles of operation flash memory combines eeprom functionality with in-circuit electrical program and erase capability. the smart 3 advanced boot block flash memory family utilizes a command user interface (cui) and automated algorithms to simplify program and erase operations. the cui allows for 100% cmos-level control inputs and fixed power supplies during erasure and programming.
smart 3 advanced boot block e 12 preliminary when v pp < v pplk , the device will only execute the following commands successfully: read array, read status register, clear status register and read identifier. the device provides standard eeprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the cui. all functions associated with altering memory contents, namely program and erase, are accessible via the cui. the internal write state machine (wsm) completely automates program and erase operations while the cui signals the start of an operation and the status register reports status. the cui handles the we# interface to the data and address latches, as well as system status requests during wsm operation. 3.1 bus operation smart 3 advanced boot block flash memory devices read, program and erase in- system via the local cpu or microcontroller. all bus cycles to or from the flash memory conform to standard microcontroller bus cycles. four control pins dictate the data flow in and out of the flash component: ce#, oe#, we# and rp#. these bus operations are summarized in table 3. table 3. bus operations (1) mode note rp# ce# oe# we# dq 0 C7 dq 8C15 read (array, status, or identifier) 2 C4 v ih v il v il v ih d out d out output disable 2 v ih v il v ih v ih high z high z standby 2 v ih v ih x x high z high z reset 2, 7 v il x x x high z high z write 2, 5C7 v ih v il v ih v il d in d in notes: 1. 8-bit devices use only dq[0:7], 16-bit devices use dq[0:15] 2. x must be v il , v ih for control pins and addresses. 3. see dc characteristics for v pplk , v pp1 , v pp2 , v pp3 , v pp4 voltages. 4. manufacturer and device codes may also be accessed in read identifier mode (a 1 Ca 21 = 0). see table 4. 5. refer to table 6 for valid d in during a write operation. 6. to program or erase the lockable blocks, hold wp# at v ih . 7. rp# must be at gnd 0.2 v to meet the maximum deep power-down current specified.
e smart 3 advanced boot block 13 preliminary 3.1.1 read the flash memory has four read modes available: read array, read identifier, read status and read query. these modes are accessible independent of the v pp voltage. the appropriate read mode command must be issued to the cui to enter the corresponding mode. upon initial device power - up or after exit from reset, the device automatically defaults to read array mode. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control; when active it enables the flash memory device. oe# is the data output control and it drives the selected memory data onto the i/o bus. for all read modes, we# and rp# must be at v ih . figure 7 illustrates a read cycle. 3.1.2 output disable with oe# at a logic - high level (v ih ), the device outputs are disabled. output pins are placed in a high - impedance state. 3.1.3 standby deselecting the device by bringing ce# to a logic - high level (v ih ) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. in standby, outputs are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 deep power-down / reset from read mode, rp# at v il for time t plph deselects the memory, places output drivers in a high - impedance state, and turns off all internal circuits. after return from reset, a time t phqv is required until the initial read access outputs are valid. a delay (t phwl or t phel ) is required after return from reset before a write can be initiated. after this wake - up interval, normal operation is restored. the cui resets to read array mode, and the status register is set to 80h. this case is shown in figure 9a. if rp# is taken low for time t plph during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. the abort process goes through the following sequence: when rp# goes low, the device shuts down the operation in progress, a process which takes time t plrh to complete. after this time t plrh , the part will either reset to read array mode (if rp# has gone high during t plrh , figure 9b) or enter reset mode (if rp# is still logic low after t plrh , figure 9c). in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl /t phel must be waited before a read or write operation is initiated, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when rp# goes high. as with any automated device, it is important to assert rp# during system reset. w hen the system comes out of reset, processor expects to read from the flash memory. automated flash memories provide status information when read during program or block erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 3.1.5 write a write takes place when both ce# and we# are low and oe# is high. commands are written to the command user interface (cui) using standard microprocessor write timings to control flash operations. the cui does not occupy an addressable memory location. the address and data buses are latched on the rising edge of the second we# or ce# pulse, whichever occurs first. figure 8 illustrates a program and erase operation. the available commands are shown in table 6, and appendix a provides detailed information on moving between the different modes of operation using cui commands.
smart 3 advanced boot block e 14 preliminary there are two commands that modify array data: program (40h) and erase (20h). writing either of these commands to the internal command user interface (cui) initiates a sequence of internally - timed functions that culminate in the completion of the requested task (unless that operation is aborted by either rp# being driven to v il for t plrh or an appropriate suspend command). 3.2 modes of operation the flash memory has four read modes and two write modes. the read modes are read array, read identifier, read status and read query (see appendix c). the write modes are program and block erase. three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. these modes are reached using the commands summarized in table 4. a comprehensive chart showing the state transitions is in appendix a. 3.2.1 read array when rp# transitions from v il (reset) to v ih , the device defaults to read array mode and will respond to the read control inputs (ce#, address inputs, and oe#) without any additional cui commands. when the device is in read array mode, four control signals control data output: we# must be logic high (v ih ) ce# must be logic low (v il ) oe# must be logic low (v il ) rp# must be logic high (v ih ) in addition, the address of the desired location must be applied to the address pins. if the device is not in read array mode, as would be the case after a program or erase operation, the read array command (ffh) must be written to the cui before array reads can take place. table 4. command codes and descriptions code device mode description 00, 01, 60, 2f, c0, 98 invalid/ reserved unassigned commands that should not be used. intel reserves the right to redefine these codes for future functions. ff read array places the device in read array mode, such that array data will be output on the data pins. 40 program set-up this is a two-cycle command. the first cycle prepares the cui for a program operation. the second cycle latches addresses and data information and initiates the wsm to execute the program algorithm. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 3.2.4. 10 alternate program set-up (see 40h/program set-up) 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will (a) set both sr.4 and sr.5 of the status register to a 1, (b) place the device into the read status register mode, and (c) wait for another command. see section 3.2.5.
e smart 3 advanced boot block 15 preliminary table 4. command codes and descriptions (continued) code device mode description d0 erase confirm program / erase resume if the previous command was an erase set-up command, then the cui will close the address and data latches, and begin erasing the block indicated on the address pins. during erase, the device will only respond to the read status register and erase suspend commands. the device will output status register data when ce# or oe# is toggled. if a program or erase operation was previously suspended, this command will resume that operation b0 program / erase suspend issuing this command will begin to suspend the currently executing program/erase operation. the status register will indicate when the operation has been successfully suspended by setting either the program suspend (sr.2) or erase suspend (sr.6) and the wsm status bit (sr.7) to a 1 (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input control pins except rp#, which will immediately shut down the wsm and the remainder of the chip if it is driven to v il . see sections 3.2.4.1 and 3.2.5.1. 70 read status register this command places the device into read status register mode. reading the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after a program or erase operation has been initiated. see section 3.2.3. 50 clear status register the wsm can set the block lock status (sr.1) , v pp status (sr.3), program status (sr.4), and erase status (sr.5) bits in the status register to 1, but it cannot clear them to 0. issuing this command clears those bits to 0. 90 read identifier puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (a 0 = 0 for manufacturer, a 0 = 1 for device, all other address inputs must be 0). see section 3.2.2. note: see appendix a for mode transition information. 3.2.2 read identifier to read the manufacturer and device codes, the device must be in read identifier mode, which can be reached by writing the read identifier command (90h). once in read identifier mode, a 0 = 0 outputs the manufacturers identification code and a 0 = 1 outputs the device identifier (see table 5) note: a 1 a 21 = 0. to return to read array mode, write the read array command (ffh). table 5. read identifier table device identifier size mfr. id -t (top boot) -b (bot. boot) 28f400b3 0089h 8894h 8895h 28f008b3 0089h d2 d3 28f800b3 8892h 8893h 28f016b3 0089h d0 d1 28f160b3 8890h 8891h 28f032b3 0089h d6 d7 28f320b3 8896 8897
smart 3 advanced boot block e 16 preliminary 3.2.3 read status register the device status register indicates when a program or erase operation is complete and the success or failure of that operation. to read the status register issue the read status register (70h) command to the cui. this causes all subsequent read operations to output data from the status register until another command is written to the cui. to return to reading from the array, issue the read array (ffh) command. the status register bits are output on dq 0 Cdq 7 . the upper byte, dq 8 Cdq 15 , outputs 00h during a read status register command. the contents of the status register are latched on the falling edge of oe# or ce#. this prevents possible bus errors which might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, sr.7 will indicate the status of the wsm; the remaining bits in the status register indicate whether or not the wsm was successful in performing the desired operation (see table 7). 3.2.3.1 clearing the status register the wsm sets status bits 1 through 7 to 1, and clears bits 2, 6 and 7 to 0, but cannot clear status bits 1 or 3 through 5 to 0. because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the clear status register (50h) command. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in s equence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note, again, that the read array command must be issued before data can be read from the memory array. 3.2.4 program mode programming is executed using a two - write sequence. the program setup command (40h) is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. programming the memory results in specific bits within an address location being changed to a 0. if the user attempts to program 1s, the memory cell contents do not change and no error occurs. the status register indicates programming status: while the program sequence executes, status bit 7 is 0. the status register can be polled by toggling either ce# or oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit sr.4 of the status register is set to indicate a program failure. if sr.3 is set then v pp was not within acceptable limits, and the wsm did not execute the program command. if sr.1 is set, a program operation was attempted on a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read array mode. 3.2.4.1 suspending and resuming program the program suspend halts the in-progress program operation to read data from another location of memory. once the programming process starts, writing the program suspend command to the cui requests that the wsm suspend the program sequence (at predetermined points in the program algorithm). the device continues to output status register data after the program suspend command is written. polling status register bits sr.7 and sr.2 will determine when the program operation has been suspended (both will be set to 1). t whrh1 /t ehrh1 specify the program suspend latency.
e smart 3 advanced boot block 17 preliminary a read array command can now be written to the cui to read data from blo cks other t han that which is suspended. the only other valid commands while program is suspended, are read status register, read identifier, and program resume. after the program resume command is written to the flash memory, the wsm will continue with the program process and status register bits sr.2 and sr.7 will automatically be cleared. after the program resume command is written, the device automatically outputs status register data when read (see appendix f for program suspend and resume flowchart ). v pp must remain at the same v pp level used for program while in program suspend mode. rp# must also remain at v ih. 3.2.5 erase mode to erase a block, write the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. only one block can be erased at a time. the wsm will execute a sequence of internally-timed events to program all bits within the block to 0, erase all bits within the block to 1, then verify that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is a 0. when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr.5 of the status register will be set to a 1, indicating an erase failure. if v pp was not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr.5 of the status register is set to indicate an erase error, and sr.3 is set to a 1 to identify that v pp supply voltage was not within acceptable limits. after an erase operation, clear the status register (50h) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. 3.2.5.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. once the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pause the erase sequence at a predetermined point in the erase algorithm. the status register will indicate if/when the erase operation has been suspended. a read array/program command can now be written to the cui in order to read data from/ program data to blocks other t han the one currently suspended. the program command can subsequently be suspended to read yet another array location. the only valid commands while erase is suspended are erase resume, program, read array, read status register, or read identifier. during erase suspend mode, the chip can be placed in a pseudo-standby mode by taking ce# to v ih . this reduces active current consumption. erase resume continues the erase sequence when ce# = v il . as with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued.
smart 3 advanced boot block e 18 preliminary table 6. command bus definitions (1, 4) first bus cycle second bus cycle command notes oper addr data oper addr data read array write x ffh read identifier 2 write x 90h read ia id read status register write x 70h read x srd clear status register write x 50h program 3 write x 40h / 10h write pa pd block erase/confirm write x 20h write ba d0h program/erase suspend write x b0h program/erase resume write x d0h notes: pa: program address pd: program data ba: block address ia: identifier address id: identifier data srd: status register data 1. bus operations are defined in table 3. 2. following the intelligent identifier command, two read operations access manufacturer and device codes. a 0 = 0 for manufacturer code, a 0 = 1 for device code. a 1 a 21 = 0. 3. either 40h or 10h command is valid although the standard is 40h. 4. when writing commands to the device, the upper data bus [dq 8 Cdq 15 ] should be either v il or v ih , to minimize current draw.
e smart 3 advanced boot block 19 preliminary table 7. status register bit definition wsms ess es ps vpps pss bls r 76543210 notes: sr.7 = write state machine status (wsms) 1 = ready 0 = busy check write state machine bit first to determine word program or block erase completion, before checking program or erase status bits. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set at 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase when this bit is set to 1, wsm has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. sr.4 = program status (ps) 1 = error in word program 0 = successful word program when this bit is set to 1, wsm has attempted but failed to program a word. sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered, and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. the v pp status bit is not guaranteed to report accurate feedback between v pplk max and v pp1 min or between v pp1 max and v pp4 min. sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to 1. pss bit remains set to 1 until a program resume command is issued. sr.1 = block lock status 1 = program/erase attempted on locked block; operation aborted 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr.0 = reserved for future enhancements (r) this bit is reserved for future use and should be masked out when polling the status register.
smart 3 advanced boot block e 20 preliminary 3.3 block locking the smart 3 advanced boot block flash memory architecture features two hardware-lockable parameter blocks. 3.3.1 wp# = v il for block locking the lockable blocks are locked w hen wp# = v il ; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two parameter blocks (blocks #69 and #70, blo cks #37 and #38 for the 16-mbit, blo cks #21 and #22 for the 8-mbit, blocks #13 and #14 for the 4-mbit) are lockable. for the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 4-/8-/ 16-/32-mbit) are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 3.3.2 wp# = v ih for block unlocking wp# = v ih unlocks all lockable blocks. these blocks can now be programmed or erased. note that rp# does not override wp# locking as in previous boot block devices. wp# controls all block locking and v pp provides protection against spurious writes. table 8 defines the write protection methods. table 8. write protection truth table for advanced boot block flash memory family v pp wp# rp# write protection provided xxv il all blocks locked v il xv ih all blocks locked 3 v pplk v il v ih lockable blocks locked 3 v pplk v ih v ih all blocks unlocked 3.4 v pp program and erase voltages intels smart 3 products provide in- system programming and erase at 2.7 v. for customers requiring fast programming in their manufacturing environment, smart 3 includes an additional low- cost 12 v programming feature. the 12 v v pp mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. during read operations or idle times, v pp may be tied to a 5 v supply. for program and erase operations, a 5 v supply is not permitted. the v pp must be supplied with either 2.7 vC3.6 v or 11.4 vC 12.6 v during program and erase operations. 3.4.1 v pp = v il for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. when v pp is below v pplk , any program or erase operation will result in a error, prompting the corresponding status register bit (sr.3) to be set. 3.5 power consumption intel? flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is selected but idle. if the ce# is deasserted, the flash enters its standby mode, where current consumption is even lower. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption.
e smart 3 advanced boot block 21 preliminary 3.5.1 active power with ce# at a logic - low level and rp# at a logic - high level, the device is in the active mode. refer to the dc characteristic tables for i cc current values. active power is the largest contributor to overall system power consumption. minimizing the active current could have a profound effect on system power consumption, especially for battery - operated devices. 3.5.2 automatic power savings (aps) automatic power savings provides low - power operation during read mode. after data is read from the memory array and the address lines are quiescent, aps circuitry places the device in a mode where typical current is comparable to i ccs ., the flash stays in this static state with outputs valid until a new location is read. 3.5.3 standby power with ce# at a logic - high level (v ih ) and device in read mode, the flash memory is in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the status of the oe# signal. if ce# transitions to a logic - high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this will provide a more accurate measure of application - specific power and energy requirements. 3.5.4 deep power-down mode the deep power-down mode is activated when rp# = v il (gnd 0.2 v). during read modes, rp# going low de-selects the memory and places the outputs in a high impedance state. recovery from deep power-down requires a minimum time of t phqv (see ac characteristics read operations ). during program or erase modes, rp# transitioning low will abort the in-progress operation. the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. during deep power-down, all internal circuits are switched to a low power savings mode (rp# transitioning to v il or turning off power to the device clears the status register). 3.6 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp or v cc , powers-up first. 3.6.1 rp# connected to system reset the use of rp# during system reset is important with automated program/erase devices since the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rp# to the system cpu reset# si gnal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko . since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two- step command sequences. the device is also disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powerg ood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.2 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from reset mode or after v cc transitions above v lko (lockout voltage), is read array mode.
smart 3 advanced boot block e 22 preliminary after any program or block erase operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. 3.7 power supply decoupling flash memorys power switching characteristics require careful device decoupling. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. read current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.
e smart 3 advanced boot block 23 preliminary 4.0 electrical specifications 4.1 absolute maximum ratings* extended operating temperature during read .......................... C40 c to +85 c during block erase and program.......................... C40 c to +85 c temperature under bias ....... C40 c to +85 c storage temperature................. C65 c to +125 c voltage on any pin (except v cc , v ccq and v pp ) with respect to gnd ............. C0.5 v to 3.7 v (1) v pp voltage (for block erase and program) with respect to gnd ..... C0.5 v to +13.5 v (1,2,4) v cc and v ccq supply voltage with respect to gnd ........... C0.2 v to +3.7 v (5) output short circuit current.....................100 ma (3) notice: this datasheet contains preliminary information on new products in production. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc voltage is C0.5 v on input/output pins, with allowable undershoot to C2.0 v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5 v, with allowable overshoot to v cc + 1.5 v for periods < 20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. v pp program voltage is normally 2.7 vC3.6 v. 5. minimum dc voltage is C0.5 v on v cc and v ccq , with allowable undershoot to C2.0 v for periods < 20 ns. maximum dc voltage on v cc and v ccq pins is v cc + 0.5 v, with allowable overshoot to v cc + 1.5 v for periods < 20 ns.
smart 3 advanced boot block e 24 preliminary 4.2 operating conditions symbol parameter notes min max units t a operating temperature C40 +85 c v cc1 v cc supply voltage 1 2.7 3.6 volts v cc2 2.7 2.85 v cc3 2.7 3.3 v ccq1 i/o supply voltage 1 2.7 3.6 volts v ccq2 1.65 2.5 v ccq3 1.8 2.5 v pp1 program and erase voltage 1 2.7 3.6 volts v pp2 2.7 2.85 v pp3 2.7 3.3 v pp4 2, 3 11.4 12.6 cycling block erase cycling 3 100,000 cycles notes: 1. v cc1 , v ccq1 , and v pp3 must share the same supply when all three are between 2.7 v and 3.6 v. 2. during read operations or idle time, 5 v may be applied to v pp indefinitely. v pp must be at valid levels for program and erase operations 3. applying v pp = 11.4 v C12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. see section 3.4 for details. 4.3 capacitance t a = 25 c, f = 1 mhz sym parameter notes typ max units conditions c in input capacitance 1 6 8 pf v in = 0 v c out output capacitance 1 10 12 pf v out = 0 v note: 1. sampled, not 100% tested.
e smart 3 advanced boot block 25 preliminary 4.4 dc characteristics (1) v cc 2.7 v C3.6 v 2.7 vC2.85 v 2.7 vC3.3 v v ccq 2.7 vC3.6 v 1.65 vC2.5 v 1.8 vC2.5 v sym parameter note typ max typ max typ max unit test conditions i li input load current 6 1 1 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 6 10 10 10 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current 6 18 35 20 50 150 250 a v cc = v cc max ce# = rp# = v cc or during program/ erase suspend i ccd v cc power-down current 6 7 20 7 20 7 20 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd rp# = gnd 0.2 v i ccr v cc read current 4,6 10 18 8 15 9 15 ma v cc = v cc max v ccq = v ccq max oe# = v ih , ce# =v il f = 5 mhz, i out =0ma inputs = v il or v ih i ppd v pp deep power- down current 0.2 5 0.2 5 0.2 5 a rp# = gnd 0.2 v v pp v cc i ppr v pp read current 2 15 2 15 2 15 a v pp v cc 3 50 200 50 200 50 200 a v pp > v cc i ccw+ i ppw v cc + v pp program current 3,6 18 55 18 55 18 55 ma v pp =v pp1, 2, 3 program in progress 10 30 10 30 10 30 ma v pp = v pp4 program in progress i cce + i ppe v cc + v pp erase current 3,6 20 45 21 45 21 45 ma v pp = v pp1, 2, 3 program in progress 16 45 16 45 16 45 ma v pp = v pp4 program in progress i ppes i ppws v pp erase suspend current 3 50 200 50 200 50 200 a v pp = v pp1, 2, 3, 4 program or erase suspend in progress
smart 3 advanced boot block e 26 preliminary 4.4 dc characteristics (continued) v cc 2.7 v C3.6 v 2.7 vC2.85 v 2.7 vC3.3 v v ccq 2.7 vC3.6 v 1.65 vC2.5 v 1.8 vC2.5 v sym parameter note min max min max min max unit test conditions v il input low voltage C0.4 0.4 C0.2 0.2 C0.2 0.2 v v ih input high voltage v ccq C0.4v v ccq C0.2v v ccq C0.2v v v ol output low voltage 0.10 -0.10 0.10 -0.10 0.10 v v cc = v cc min v ccq = v ccq min i ol = 100 m a v oh output high voltage v ccq C0.1v v ccq C0.1v v ccq C0.1v vv cc = v cc min v ccq = v ccq min i oh = C100 m a v pplk v pp lock-out voltage 2 1.5 1.5 1.5 v complete write protection v pp1 v pp during 2 2.7 3.6 v v pp2 program and 2 2.7 2.85 v v pp3 erase operations 2 2.7 3.3 v v pp4 2,5 11.4 12.6 11.4 12.6 11.4 12.6 v v lko v cc prog/erase lock voltage 1.5 1.5 1.5 v v lko2 v ccq prog/erase lock voltage 1.2 1.2 1.2 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc , t a = +25 c. 2. erase and program are inhibited when v pp < v pplk and not guaranteed outside the valid v pp ranges of v pp1 , v pp2 , v pp3 and v pp4. for read operations or during idle time, a 5 v supply may be applied to v pp indefinitely. however, v pp must be at valid levels for program and erase operations. 3. sampled, not 100% tested. 4. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation. 5. applying v pp = 11.4 vC12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. see section 3.4 for details. for read operations or during idle time, a 5 v supply may be applied to v pp indefinitely. however, v pp must be at valid levels for program and erase operations. 6. since each column lists specifications for a different v cc and v ccq voltage range combination, the test conditions v cc max, v ccq max, v cc min, and v ccq min refer to the maximum or minimum v cc or v ccq voltage listed at the top of each column.
e smart 3 advanced boot block 27 preliminary test points input output v ccq 0.0 v ccq 2 v ccq 2 0580_05 note: ac test inputs are driven at v ccq for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10%C90%) <10 ns. worst case speed conditions are when v ccq = v ccq min. figure 5. input range and measurement points c l out v ccq device under test r 1 r 2 0580_06 note: see table for component values. figure 6. test configuration test configuration component values for worst case speed conditions test configuration c l (pf) r 1 ( w )r 2 ( w ) v ccq1 standard test 50 25 k 25 k v ccq2 standard test 50 16.7 k 16.7 k note: c l includes jig capacitance.
smart 3 advanced boot block e 28 preliminary 4.5 ac characteristics read operations (1) product 3.0 v C3.6 v 80 ns 100 ns 2.7 vC3.6 v 90 ns 110 ns # sym parameter note min max min max min max min max unit r1 t avav read cycle time 80 90 100 110 ns r2 t avqv address to output delay 80 90 100 110 ns r3 t elqv ce# to output delay 2 80 90 100 110 ns r4 t glqv oe# to output delay 2 30303030ns r5 t phqv rp# to output delay 600 600 600 600 ns r6 t elqx ce# to output in low z 30000ns r7 t glqx oe# to output in low z 30000ns r8 t ehqz ce# to output in high z 3 25252525ns r9 t ghqz oe# to output in high z 3 25252525ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 30000ns notes: 1. see ac waveform: read operations . 2. oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 3. sampled, but not 100% tested.
e smart 3 advanced boot block 29 preliminary address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v high z valid output data valid standby high z r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 0580_07 figure 7. ac waveform: read operations
smart 3 advanced boot block e 30 preliminary 4.6 ac characteristics write operations (1) product 3.0 v C 3.6 v 80 100 2.7 v C 3.6 v 90 110 # symbol parameter note min min min min unit w1 t phwl / t phel rp# high recovery to we# (ce#) going low 600 600 600 600 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 0000ns w3 t eleh / t wlwh we# (ce#) pulse width 4 70 70 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2 50506060ns w5 t avwh / t aveh address setup to we# (ce#) going high 2 70707070ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 0000ns w7 t whdx / t ehdx data hold time from we# (ce#) high 20000ns w8 t whax / t ehax address hold time from we# (ce#) high 20000ns w9 t whwl / t ehel we# (ce#) pulse width high 4 30 30 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3 200 200 200 200 ns w11 t qvvl v pp hold from valid srd 30000ns notes: 1. read timing characteristics during program suspend and erase suspend are the same as during read-only operations. 2. refer to command definition table (table 6) for valid a in or d in . 3. sampled, but not 100% tested. 4. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl .
e smart 3 advanced boot block 31 preliminary 4.7 program and erase timings v pp 2.7 v C3.6 v 11.4 vC12.6 v symbol parameter notes typ (1) max typ (1) max units t bwpb 8-kb parameter block program time (byte) 2, 3 0.16 0.48 0.08 0.24 s 4-kw parameter block program time (word) 2, 3 0.10 0.30 0.03 0.12 s t bwmb 64-kb main block program time (byte) 2, 3 1.2 3.7 0.6 1.7 s 32-kw main block program time(word) 2, 3 0.8 2.4 0.24 1 s t whqv1 / t ehqv1 byte program time 2, 3 17 165 8 185 s word program time 2, 3 22 200 8 185 s t whqv2 / t ehqv2 8-kb parameter block erase time (byte) 2, 3 1 4 0.8 4 s 4-kw parameter block erase time (word) 2, 3 0.5 4 0.4 4 s t whqv3 / t ehqv3 64-kb main block erase time (byte) 2, 3 1 5 1 5 s 32-kw main block erase time (word) 2, 3 1 5 0.6 5 s t whrh1 / t ehrh1 program suspend latency 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 5 20 5 20 s notes: 1. typical values measured at nominal voltages and t a = +25 c. 2. excludes external system-level overhead. 3. sampled, not 100% tested.
smart 3 advanced boot block e 32 preliminary addresses [a] ce#(we#) [e(w)] oe# [g] we#(ce#) [w(e)] data [d/q] rp# [p] ih v il v ih v il v ih v il v ih v il v il v il v in d in a in a valid srd in d ih v high z ih v il v v [v] pp pph v pplk v pph v1 2 wp# il v ih v in d ab c d e f w8 w6 w9 w3 w4 w7 w1 w5 w2 w10 w11 (note 1) (note 1) 0580_08 notes: 1. ce# must be toggled low when reading status register data. we# must be inactive (high) when reading status register data. a. v cc power-up and standby. b. write program or erase setup command. c. write valid address and data (for program) or erase confirm command. d. automated program or erase delay. e. read status register data (srd): reflects completed program/erase operation. f. write read array command. figure 8. ac waveform: program and erase operations
e smart 3 advanced boot block 33 preliminary 5.0 reset operations ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plrh t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t 0580_09 figure 9. ac waveform: deep power-down/reset operation reset specifications v cc = 2.7 v C3.6 v symbol parameter notes min max unit t plph rp# low to reset during read (if rp# is tied to v cc , this specification is not applicable) 1,3 100 ns t plrh rp# low to reset during block erase or program 2,3 22 s notes: 1. if t plph is <100 ns the device may still reset but this is not guaranteed. 2. if rp# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 3. sampled, but not 100% tested.
smart 3 advanced boot block e 34 preliminary 6.0 ordering information t e 2 8 f 1 6 0 b 3 t a 9 0 package te = 40-lead/48-lead tsop gt = 48-ball bga* csp product line designator for all intel flash products access speed (ns) (90, 110) product family b3 = smart 3 advanced boot block v cc = 2.7 v - 3.6 v v pp = 2.7 v - 3.6 v or 11.4 v - 12.6 v device density 320 = x16 (32 mbit) 160 = x16 (16 mbit) 800 = x16 (8 mbit) 400 = x 16 (4 mbit) 032 = x 8 (32 mbit) 016 = x8 (16 mbit) 008 = x8 (8 mbit) t = top blocking b = bottom blocking lithography not present = 0.4 m a = 0.25 m
e smart 3 advanced boot block 35 preliminary ordering information valid combinations 40-lead tsop 48-ball bga* csp (1) 48-lead tsop 48-ball bga csp ext. temp. gt28f032b3ta95 te28f320b3ta95 gt28f320b3ta95 32 m gt28f032b3ba95 te28f320b3ba95 gt28f320b3ba95 gt28f032b3ta115 te28f320b3ta115 gt28f320b3ta115 gt28f032b3ba115 te28f320b3ba115 gt28f320b3ba115 ext. temp. te28f016b3ta90 (2) gt28f016b3ta90 (2) te28f160b3ta90 (2) gt28f160b3ta90 (2) 16 m te28f016b3ba90 (2) gt28f016b3ba90 (2) te28f160b3ba90 (2) gt28f160b3ba90 (2) te28f016b3ta110 (2) gt28f016b3ta110 (2) te28f160b3ta110 (2) gt28f160b3ta110 (2) te28f016b3ba110 (2) gt28f016b3ba110 (2) te28f160b3ba110 (2) gt28f160b3ba110 (2) ext. temp. te28f008b3ta90 (2) gt28f008b3t90 te28f800b3ta90 (2) gt28f800b3t90 8 m te28f008b3ba90 (2) gt28f008b3b90 te28f800b3ba90 (2) gt28f800b3b90 te28f008b3ta110 (2) gt28f008b3t110 te28f800b3ta110 (2) gt28f800b3t110 te28f008b3ba110 (2) gt28f008b3b110 te28f800b3ba110 (2) gt28f800b3b110 ext. temp te28f400b3t110 4 m te28f400b3b110 notes: 1. the 48-ball bga package top side mark reads f160b3 [or f800b3]. this mark is identical for both x8 and x16 products. all product shipping boxes or trays provide the correct information regarding bus architecture. however, once the devices are removed from the shipping media, it may be difficult to differentiate based on the top side mark. the device identifier (accessible through the device id command: see section 3.2.2 for further details) enables x8 and x16 bga package product differentiation. 2. the second line of the 48-ball bga package top side mark specifies assembly codes. for samples only, the first character signifies either e for engineering samples or s for silicon daisy chain samples. all other assembly codes without an e or s as the first character are production units. 3. product can be ordered in either 0.25 m or 0.4 m material. the a before the access speed specifies 0.25 m material. 4. for new designs, intel recommends using 0.25 m advanced boot block devices.
smart 3 advanced boot block e 36 preliminary 7.0 additional information (1,2) order number document/tool 210830 1997 flash memory databook 297948 smart 3 advanced boot block flash memory family specification update 297835 28f160b3 specification update smart 3 advanced boot block algorithms (c and assembly) http://developer.intel.com/design/flcomp contact your intel representative flash data integrator (fdi) software developers kit 297874 fdi interactive: play with intels flash data integrator on your pc note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com or http://developer.intel.com for technical documentation and tools.
e smart 3 advanced boot block 37 preliminary appendix a write state machine current/next states command input (and next state) current state sr.7 data when read read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h) read identifier. (90h) read array 1 array read array program setup erase setup read array read status read array read identifier read status 1 status read array program setup erase setup read array read status read array read identifier read identifier 1 identifier read array program setup erase setup read array read status read array read identifier prog. setup 1 status program (command input = data to be programmed) program (continue) 0 status program (continue) prog. susp. to rd. status program (continue) program suspend to read status 1 status prog. sus. to read array program suspend to read array program (continue) program susp. to read array program (continue) prog. susp. to read status prog. sus. to read array prog. susp. to read identifier program suspend to read array 1 array prog. susp. to read array program suspend to read array program (continue) program susp. to read array program (continue) prog. susp. to read status prog. sus. to read array prog. susp. to read identifier prog. susp. to read identifier 1 identifier prog. susp. to read array program suspend to read array program (continue) program susp. to read array program (continue) prog. susp. to read status prog. sus. to read array prog. susp. to read identifier program (complete) 1 status read array program setup erase setup read array read status read array read identifier erase setup 1 status erase command error erase (continue) erase cmd. error erase (continue) erase command error erase cmd. error 1 status read array program setup erase setup read array read status read array read identifier erase (continue) 0 status erase (continue) erase sus. to read status erase (continue) erase suspend to status 1 status erase susp. to read array program setup erase susp. to read array erase erase susp. to read array erase erase susp. to read status erase susp. to read array ers. susp. to read identifier erase susp. to read array 1 array erase susp. to read array program setup erase susp. to read array erase erase susp. to read array erase erase susp. to read status erase susp. to read array ers. susp. to read identifier erase susp. to read identifier 1 identifier erase susp. to read array program setup erase susp. to read array erase erase susp. to read array erase erase susp. to read status erase susp. to read array ers. susp. to read identifier erase (complete) 1 status read array program setup erase setup read array read status read array read identifier
smart 3 advanced boot block e 38 preliminary appendix b access time vs. capacitive load (t avqv vs. c l ) access time vs. load capacitance 75 79 83 87 91 95 99 30 40 50 60 70 80 90 100 load capacitance (pf) access time (ns) vccq = 2.7v vccq = 3.0v this chart shows a derating curve for device access time with respect to capacitive load. the value in the dc characteristics section of the specification corresponds to c l = 50 pf. note: sampled, but not 100% tested
e smart 3 advanced boot block 39 preliminary appendix c architecture block diagram output multiplexer 4-kword parameter block 32-kword main block 32-kword main block 4-kword parameter block y-gating/sensing write state machine program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder power reduction control input buffer output buffer gnd v cc v pp ce# we# oe# rp# command user interface input buffer a 0 -a 19 dq 0 -dq 15 v ccq wp# 0580-c1
smart 3 advanced boot block e 40 preliminary appendix d word-wide memory map diagrams 8-mbit, 16-mbit, and 32-mbit word-wide memory addressing top boot bottom boot size (kw) 8m 16m 32m size (kw) 8m 16m 32m 4 7f000-7ffff ff000-fffff 1ff000-1fffff 32 1f8000-1fffff 4 7e000-7efff fe000-fefff 1fe000-1fefff 32 1f0000-1f7fff 4 7d000-7dfff fd000-fdfff 1fd000-1fdfff 32 1e8000-1effff 4 7c000-7cfff fc000-fcfff 1fc000-1fcfff 32 1e0000-1e7fff 4 7b000-7bfff fb000-fbfff 1fb000-1fbfff 32 1d8000-1dffff 4 7a000-7afff fa000-fafff 1fa000-1fafff 32 1d0000-1d7fff 4 79000-79fff f9000-f9fff 1f9000-1f9fff 32 1c8000-1cffff 4 78000-78fff f8000-f8fff 1f8000-1f8fff 32 1c0000-1c7fff 32 70000-77fff f0000-f7fff 1f0000-1f7fff 32 1b8000-1bffff 32 68000-6ffff e8000-effff 1e8000-1effff 32 1b0000-1b7fff 32 60000-67fff e0000-e7fff 1e0000-1e7fff 32 1a8000-1affff 32 58000-5ffff d8000-dffff 1d8000-1dffff 32 1a0000-1a7fff 32 50000-57fff d0000-d7fff 1d0000-1d7fff 32 198000-19ffff 32 48000-4ffff c8000-cffff 1c8000-1cffff 32 190000-197fff 32 40000-47fff c0000-c7fff 1c0000-1c7fff 32 188000-18ffff 32 38000-3ffff b8000-bffff 1b8000-1bffff 32 180000-187fff 32 30000-37fff b0000-b7fff 1b0000-1b7fff 32 178000-17ffff 32 28000-2ffff a8000-affff 1a8000-1affff 32 170000-177fff 32 20000-27fff a0000-a7fff 1a0000-1a7fff 32 168000-16ffff 32 18000-1ffff 98000-9ffff 198000-19ffff 32 160000-167fff 32 10000-17fff 90000-97fff 190000-197fff 32 158000-15ffff 32 08000-0ffff 88000-8ffff 188000-18ffff 32 150000-157fff 32 00000-07fff 80000-87fff 180000-187fff 32 148000-14ffff 32 78000-7ffff 178000-17ffff 32 140000-147fff 32 70000-77fff 170000-177fff 32 138000-13ffff 32 68000-6ffff 168000-16ffff 32 130000-137fff 32 60000-67fff 160000-167fff 32 128000-12ffff 32 58000-5ffff 158000-15ffff 32 120000-127fff 32 50000-57fff 150000-157fff 32 118000-11ffff 32 48000-4ffff 148000-14ffff 32 110000-117fff 32 40000-47fff 140000-147fff 32 108000-10ffff 32 38000-3ffff 138000-13ffff 32 100000-107fff 32 30000-37fff 130000-137fff 32 f8000-fffff 0f8000-0fffff 32 28000-2ffff 128000-12ffff 32 f0000-f7fff 0f0000-0f7fff 32 20000-27fff 120000-127fff 32 e8000-effff 0e8000-0effff 32 18000-1ffff 118000-11ffff 32 e0000-e7fff 0e0000-0e7fff 32 10000-17fff 110000-117fff 32 d8000-dffff 0d8000-0dffff 32 08000-0ffff 108000-10ffff 32 d0000-d7fff 0d0000-0d7fff 32 00000-07fff 100000-107fff 32 c8000-cffff 0c8000-0cffff this column continues on next page this column continues on next page
e smart 3 advanced boot block 41 preliminary 8-mbit, 16-mbit, and 32-mbit word-wide memory addressing (continued) top boot bottom boot size (kw) 8m 16m 32m size (kw) 8m 16m 32m 32 0f8000-0fffff 32 c0000-c7fff 0c0000-0c7fff 32 0f0000-0f7fff 32 b8000-bffff 0b8000-0bffff 32 0e8000-0effff 32 b0000-b7fff 0b0000-0b7fff 32 0e0000-0e7fff 32 a8000-affff 0a8000-0affff 32 0d8000-0dffff 32 a0000-a7fff 0a0000-0a7fff 32 0d0000-0d7fff 32 98000-9ffff 098000-09ffff 32 0c8000-0cffff 32 90000-97fff 090000-097fff 32 0c0000-0c7fff 32 88000-8ffff 088000-08ffff 32 0b8000-0bffff 32 80000-87fff 080000-087fff 32 0b0000-0b7fff 32 78000-7ffff 78000-7ffff 78000-7ffff 32 0a8000-0affff 32 70000-77fff 70000-77fff 70000-77fff 32 0a0000-0a7fff 32 68000-6ffff 68000-6ffff 68000-6ffff 32 098000-09ffff 32 60000-67fff 60000-67fff 60000-67fff 32 090000-097fff 32 58000-5ffff 58000-5ffff 58000-5ffff 32 088000-08ffff 32 50000-57fff 50000-57fff 50000-57fff 32 080000-087fff 32 48000-4ffff 48000-4ffff 48000-4ffff 32 078000-07ffff 32 40000-47fff 40000-47fff 40000-47fff 32 070000-077fff 32 38000-3ffff 38000-3ffff 38000-3ffff 32 068000-06ffff 32 30000-37fff 30000-37fff 30000-37fff 32 060000-067fff 32 28000-2ffff 28000-2ffff 28000-2ffff 32 058000-05ffff 32 20000-27fff 20000-27fff 20000-27fff 32 050000-057fff 32 18000-1ffff 18000-1ffff 18000-1ffff 32 048000-04ffff 32 10000-17fff 10000-17fff 10000-17fff 32 040000-047fff 32 08000-0ffff 08000-0ffff 08000-0ffff 32 038000-03ffff 4 07000-07fff 07000-07fff 07000-07fff 32 030000-037fff 4 06000-06fff 06000-06fff 06000-06fff 32 028000-02ffff 4 05000-05fff 05000-05fff 05000-05fff 32 020000-027fff 4 04000-04fff 04000-04fff 04000-04fff 32 018000-01ffff 4 03000-03fff 03000-03fff 03000-03fff 32 010000-017fff 4 02000-02fff 02000-02fff 02000-02fff 32 008000-00ffff 4 01000-01fff 01000-01fff 01000-01fff 32 000000-007fff 4 00000-00fff 00000-00fff 00000-00fff
smart 3 advanced boot block e 42 preliminary 4-mbit word-wide memory addressing top boot bottom boot size (kw) 4m size (kw) 4m 4 3f000-3ffff 32 38000-3ffff 4 3e000-3efff 32 30000-37fff 4 3d000-3dfff 32 28000-2ffff 4 3c000-3cfff 32 20000-27fff 4 3b000-3bfff 32 18000-1ffff 4 3a000-3afff 32 10000-017fff 4 39000-39fff 32 08000-0ffff 4 38000-38fff 4 07000-07fff 32 30000-037fff 4 06000-06fff 32 28000-2ffff 4 05000-05fff 32 20000-2ffff 4 04000-04fff 32 18000-1ffff 4 03000-03fff 32 10000-017fff 4 02000-02fff 32 08000-0ffff 4 01000-01fff 32 00000-07fff 4 00000-00fff
e smart 3 advanced boot block 43 preliminary appendix e byte-wide memory map diagrams byte-wide memory addressing top boot bottom boot size (kb) 8m 16m 32m size (kb) 8m 16m 32m 8 fe000-fffff 1fe000-1fffff 3fe000-3fffff 64 3f0000-3fffff 8 fc000-fdfff 1fc000-1fdfff 3fc000-3fdfff 64 3e0000-3effff 8 fa000-fbfff 1fa000-1fbfff 3fa000-3fbfff 64 3d0000-3dffff 8 f8000-f9fff 1f8000-1f9fff 3f8000-3f9fff 64 3c0000-3cffff 8 f6000-f7fff 1f6000-1f7fff 3f6000-3f7fff 64 3b0000-3bffff 8 f4000-f5fff 1f4000-1f5fff 3f4000-3f5fff 64 3a0000-3affff 8 f2000-f3fff 1f2000-1f3fff 3f2000-3f3fff 64 390000-39ffff 8 f0000-f1fff 1f0000-1f1fff 3f0000-3f1fff 64 380000-38ffff 64 e0000-effff 1e0000-1effff 3e0000-3effff 64 370000-37ffff 64 d0000-dffff 1d0000-1dffff 3d0000-3dffff 64 360000-36ffff 64 c0000-cffff 1c0000-1cffff 3c0000-3cffff 64 350000-35ffff 64 b0000-bffff 1b0000-1bffff 3b0000-3bffff 64 340000-34ffff 64 a0000-affff 1a0000-1affff 3a0000-3affff 64 330000-33ffff 64 90000-9ffff 190000-19ffff 390000-39ffff 64 320000-32ffff 64 80000-8ffff 180000-18ffff 380000-38ffff 64 310000-31ffff 64 70000-7ffff 170000-17ffff 370000-37ffff 64 300000-30ffff 64 60000-6ffff 160000-16ffff 360000-36ffff 64 2f0000-2fffff 64 50000-5ffff 150000-15ffff 350000-35ffff 64 2e0000-2effff 64 40000-4ffff 140000-14ffff 340000-34ffff 64 2d0000-2dffff 64 30000-3ffff 130000-13ffff 330000-33ffff 64 2c0000-2cffff 64 20000-2ffff 120000-12ffff 320000-32ffff 64 2b0000-2bffff 64 10000-1ffff 110000-11ffff 310000-31ffff 64 2a0000-2affff 64 00000-0ffff 100000-10ffff 300000-30ffff 64 290000-29ffff 64 0f0000-0fffff 2f0000-2fffff 64 280000-28ffff 64 0e0000-0effff 2e0000-2effff 64 270000-27ffff 64 0d0000-0dffff 2d0000-2dffff 64 260000-26ffff 64 0c0000-0cffff 2c0000-2cffff 64 250000-25ffff 64 0b0000-0bffff 2b0000-2bffff 64 240000-24ffff 64 0a0000-0affff 2a0000-2affff 64 230000-23ffff 64 090000-09ffff 290000-29ffff 64 220000-22ffff 64 080000-08ffff 280000-28ffff 64 210000-21ffff 64 070000-07ffff 270000-27ffff 64 200000-20ffff 64 060000-06ffff 260000-26ffff 64 1f0000-1fffff 1f0000-1fffff 64 050000-05ffff 250000-25ffff 64 1e0000-1effff 1e0000-1effff 64 040000-04ffff 240000-24ffff 64 1d0000-1dffff 1d0000-1dffff 64 030000-03ffff 230000-23ffff 64 1c0000-1cffff 1c0000-1cffff 64 020000-02ffff 220000-22ffff 64 1b0000-1bffff 1b0000-1bffff 64 010000-01ffff 210000-21ffff 64 1a0000-1affff 1a0000-1affff 64 000000-00ffff 200000-20ffff 64 190000-19ffff 190000-19ffff this column continues on next page this column continues on next page
smart 3 advanced boot block e 44 preliminary byte-wide memory addressing (continued) top boot bottom boot size (kb) 8m 16m 32m size (kb) 8m 16m 32m 64 1f0000-1fffff 64 180000-18ffff 180000-18ffff 64 1e0000-1effff 64 170000-17ffff 170000-17ffff 64 1d0000-1dffff 64 160000-16ffff 160000-16ffff 64 1c0000-1cffff 64 150000-15ffff 150000-15ffff 64 1b0000-1bffff 64 140000-14ffff 140000-14ffff 64 1a0000-1affff 64 130000-13ffff 130000-13ffff 64 190000-19ffff 64 120000-12ffff 120000-12ffff 64 180000-18ffff 64 110000-11ffff 110000-11ffff 64 170000-17ffff 64 100000-10ffff 100000-10ffff 64 160000-16ffff 64 f0000-fffff 0f0000-0fffff 0f0000-0fffff 64 150000-15ffff 64 e0000-effff 0e0000-0effff 0e0000-0effff 64 140000-14ffff 64 d0000-dffff 0d0000-0dffff 0d0000-0dffff 64 130000-13ffff 64 c0000-cffff 0c0000-0cffff 0c0000-0cffff 64 120000-12ffff 64 b0000-bffff 0b0000-0bffff 0b0000-0bffff 64 110000-11ffff 64 a0000-affff 0a0000-0affff 0a0000-0affff 64 100000-10ffff 64 90000-9ffff 090000-09ffff 090000-09ffff 64 0f0000-0fffff 64 80000-8ffff 080000-08ffff 080000-08ffff 64 0e0000-0effff 64 70000-7ffff 070000-07ffff 070000-07ffff 64 0d0000-0dffff 64 60000-6ffff 060000-06ffff 060000-06ffff 64 0c0000-0cffff 64 50000-5ffff 050000-05ffff 050000-05ffff 64 0b0000-0bffff 64 40000-4ffff 040000-04ffff 040000-04ffff 64 0a0000-0affff 64 30000-3ffff 030000-03ffff 030000-03ffff 64 090000-09ffff 64 20000-2ffff 020000-02ffff 020000-02ffff 64 080000-08ffff 64 10000-1ffff 010000-01ffff 010000-01ffff 64 070000-07ffff 8 0e000-0ffff 00e000-00ffff 00e000-00ffff 64 060000-06ffff 8 0c000-0dfff 00c000-00dfff 00c000-00dfff 64 050000-05ffff 8 0a000-0bfff 00a000-00bfff 00a000-00bfff 64 040000-04ffff 8 08000-09fff 008000-009fff 008000-009fff 64 030000-03ffff 8 06000-07fff 006000-007fff 006000-007fff 64 020000-02ffff 8 04000-05fff 004000-005fff 004000-005fff 64 010000-01ffff 8 02000-03fff 002000-003fff 002000-003fff 64 000000-00ffff 8 00000-01fff 000000-001fff 000000-001fff
e smart 3 advanced boot block 45 preliminary appendix f program and erase flowcharts start write 40h program address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error programming error attempted program to locked block - aborted program successful sr.3 = sr.4 = sr.1 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases where multiple bytes are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1 0 1 0 1 0 command program setup program comments data = 40h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.1 1 = attempted program to locked block - program aborted read status register data toggle ce# or oe# to update status register data standby check sr.4 1 = v pp program error 0580_e1 figure 10. program flowchart
smart 3 advanced boot block e 46 preliminary start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 read array data from block other than the one being programmed. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation write write read read standby standby write command program suspend read array program resume 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write write read read standby standby write data=70h addr=x command program suspend read array program resume program suspend read status read array program resume 0580_e2 figure 11. program suspend/resume flowchart
e smart 3 advanced boot block 47 preliminary start write 20h write d0h and block address read status register sr.7 = full status check if desired block erase complete full status check procedure bus operation write write standby repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last write operation to reset device to read array mode. bus operation standby sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend erase suspend erase loop 1 0 standby command erase setup erase confirm comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pp range error command sequence error block erase successful sr.3 = sr.4,5 = 1 0 1 0 block erase error sr.5 = 1 0 attempted erase of locked block - aborted sr.1 = 1 0 read status register data toggle ce# or oe# to update status register data standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block - erase aborted 0580_e3 figure 12. block erase flowchart
smart 3 advanced boot block e 48 preliminary start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh read array data erase completed done reading yes write ffh write d0h erase resumed read array data 0 1 read array data from block other than the one being erased. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = x bus operation write write read read standby standby write command program suspend read array program resume 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write write read read standby standby write data=70h addr=x command program suspend read array program resume erase suspend read status read array erase resume 0580_e4 figure 13. erase suspend/resume flowchart

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